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MC-ACT-UL2PHY Datasheet(PDF) 3 Page - Actel Corporation

Part # MC-ACT-UL2PHY
Description  ATM cell processors ATM switch fabrics
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

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Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Direction
Description
RESET_N
Input
Active low reset.
ING_CLK
Input
Transmit Clock. See UL2 Specification for details.
ING_ADDR(4:0)
Input
Transmit Polling Address. See UL2 Specification for details.
ING_CLAV
Output
Transmit Cell Available. See UL2 Specification for details.
ING_ENB_N
Input
Transmit Enable. See UL2 Specification for Details.
ING_DATA(N:0)
Output
Transmit Data, where N is 7 + (8*SIZE_16). See UL2 Specification for details.
ING_PRTY
Output
Transmit Parity. See UL2 Specification for details.
ING_SOC
Output
Transmit Start-of-Cell. See UL2 Specification for details.
EGR_CLK
Input
Receive Clock. See UL2 Specification for details.
EGR_ADDR(4:0)
Input
Receive Polling Address. See UL2 Specification for details.
EGR_CLAV
Output
Receive Cell Available. See UL2 Specification for details.
EGR_ENB_N
Input
Receive Enable. See UL2 Specification for Details.
EGR_DATA(N:0)
Input
Receive Data, where N is 7 + (8*SIZE_16). See UL2 Specification for details.
EGR_PRTY
Input
Receive Parity. See UL2 Specification for details.
EGR_SOC
Input
Receive Start-of-Cell. See UL2 Specification for details.
WR_CLK
Input
Write Clock. Maximum Frequency is 50 MHz.
WR_DATA(M*N:0)
Input
Write Data Bus, where M*N is NUMPHYS times (8 + (8*SIZE_16)) minus one.
WR_ENB(M:0)
Input
Write Enable, where M is NUMPHYS minus one. Asserted for each write of a valid byte of a cell.
INCREMENT(M:0)
Input
Packet Counter Increment, where M is NUMPHYS minus one. Asserted on the last valid byte of a cell.
A_FULL(M:0)
Output
Almost Full, where M is NUMPHYS minus one. Asserted when the write FIFO does not have enough space for an
additional cell.
RD_CLK
Input
Read Clock. Maximum Frequency is 50 MHz.
RD_DATA(M*N:0)
Output
Read Data Bus, where M*N is NUMPHYS times (8 + (8*SIZE_16)) minus one.
RD_ENB(M:0)
Input
Read Enable, where M is NUMPHYS minus one. Asserted for each read of a valid byte of a cell. There is a one clock
latency on each read.
DECREMENT(M:0)
Input
Packet Counter Decrement, where M is NUMPHYS minus one. Asserted on the first byte read of a cell.
FLAG(M:0)
Output
Cell Available Flag, where M is NUMPHYS minus one. Asserted when there is at least one cell available to be read.
EGR_PERR
Output
Receive Data Parity Error. Asserted when a parity error was detected on the Receive Data bus.
Table 2: Utopia Level 2 PHY Signal List


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