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A500K050-BG208I Datasheet(PDF) 5 Page - Actel Corporation |
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A500K050-BG208I Datasheet(HTML) 5 Page - Actel Corporation |
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5 / 72 page  Discontinued – v3.0 5 Pr oAS I C ® 5 00K Fa mily Ro ut in g Re so u r ce s The routing structure of the ProASIC 500K devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks. The ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 4 on page 6). The efficient long line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASIC device (Figure 5 on page 6). Each tile can drive signals onto the efficient long line resources, while the resources can also access every input of any tile. The routing software automatically inserts active buffers to limit loading effects due to distance and fanout. The high speed very long line resources, spanning across the entire device with minimal delay, are used to route very long or very high fanout nets. These resources run vertically and horizontally, providing multiple access to each group of tiles throughout the device (Figure 6 on page 7). The high performance global networks’ clock trees are low skew, high fanout nets that are accessible from four dedicated pins or from internal logic (Figure 7 on page 8). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all tiles. Clo c k Reso urce s ProASIC’s high-drive routing structure provides four global networks, each accessible from either a dedicated global pad or a logic tile. Global lines provide optimized worst-case clock skew of 0.3ns. Figure 2 • Flash Switch Figure 3 • Core Logic Tile Sel 1 Sel 2 Switch In Switch Out Word Floating Gate Local Routing In 1 In 2 (CLK) In 3 (Reset) Efficient Long Line Routing |
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Similar Description - A500K050-BG208I |
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