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A500K050-PQ208ES Datasheet(PDF) 4 Page - Actel Corporation |
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A500K050-PQ208ES Datasheet(HTML) 4 Page - Actel Corporation |
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4 / 72 page  Pr oAS I C ® 500K Fa mily 4 Discontinued – v3.0 Pr oASIC 500K Archit ect ure The ProASIC 500K family’s proprietary architecture provides granularity comparable to gate arrays. Unlike SRAM-based FPGAs that utilize look-up tables or architectural mapping during design, ProASIC device designs are directly synthesized to gates. That streamlines the design flow, increases design productivity, and eliminates dependencies on vendor-specific design tools. The ProASIC 500K device core consists of a Sea-of-Tiles™(Figure 1), each of which can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (See Figure 2 on page 5 and Figure 3 on page 5). Gates and larger functions are connected with four levels of routing hierarchy. Flash memory bits are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. The ProASIC 500K devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Table 3 on page 12 lists the 24 basic memory configurations. Fl as h Swi t ch In the ProASIC Flash switch, two transistors share the floating gate which stores the programming information. One is the Flash transistor which stores programming information and in which erasing is performed. The second transistor connects/separates routing elements or configuration signal lines (Figure 2 on page 5). Lo gi c Ti l e The logic tile cell, Figure 3 on page 5, has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast local and efficient long line routing resources). Any three-input one-output logic function, except a three input XOR, can be configured as one tile. Two multiplexers with feedback paths through the NAND gates allow the tile to be configured as a latch with clear or set, or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. Figure 1 • The ProASIC Device Architecture 256x9 Two-Port SRAM or FIFO Block Logic Tile |
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