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A500K180-PQ208PP Datasheet(PDF) 9 Page - Actel Corporation |
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A500K180-PQ208PP Datasheet(HTML) 9 Page - Actel Corporation |
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9 / 72 page  Discontinued – v3.0 9 Pr oAS I C ® 5 00K Fa mily I n p u t/Ou tp ut Bl oc ks To meet complex system design needs, the ProASIC 500K family offers devices with a large number of I/O pins, up to 440 user I/O pins on the A500K270. If the I/O pad is powered at 3.3V, each I/O can be selectively configured at 2.5V and 3.3V threshold levels. Table 2 shows the available supply voltage configurations. Figure 8 illustrates I/O interfaces with other devices. The I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a three-state driver, or a bidirectional buffer (Figure 9). I/O pads configured as inputs have the following features: • Individually selectable 2.5V or 3.3V threshold levels1 • Optional pull-up resistor I/O pads configured as outputs have the following features: • Individually selectable 2.5V or 3.3V compliant output signals1 •3.3V PCI compliant • Ability to drive LVTTL and LVCMOS levels • Selectable drive strengths • Selectable slew rates • Tristate I/O pads configured as bidirectional buffers have the following features: • Individually selectable 2.5V or 3.3V compliant output signals and threshold levels1 •3.3V PCI compliant • Optional pull-up resistor • Selectable drive strengths • Selectable slew rates • Tristate All I/Os also include an ESD protection circuit. Each I/O is tested according to the following model: Boun dary S c a n ProASIC devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASIC boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 10 on page 10). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS), the optional IDCODE instructions and private instructions used for device programming and factory testing. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI, and TRST are equipped Table 2 • ProASIC Power Supply Voltages VDDP 2.5V 3.3V Input Tolerance 2.5V 3.3V, 2.5V Output Drive 2.5V 3.3V, 2.5V Note: VDDL is always 2.5V. 1. If pads are configured for 2.5V operation, they are compliant with 2.5V level signals as defined by JEDEC JESD 8-5. If pads are configured for 3.3V operation, they are compliant to the standard as defined by JEDEC JESD 8-A (LVTTL and LVCMOS). • Human Body Model (HBM) (Per Mil Std 883 Method 3015) 2000V Figure 8 • I/O Interfaces Figure 9 • I/O Block Schematic Representation ProASIC VDDL = 2.5V VDDP = 2.5V ProASIC VDDL = 2.5V VDDP = 3.3V 2.5V Device 2.5V Device 2.5V Device 3.3V Device 2.5V Device 3.3V Device 3.3V/2.5V Signal Control Pull-up Control 3.3V/2.5V Signal Control Drive Strength and Slew Rate Control Pad Y EN A |
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Similar Description - A500K180-PQ208PP |
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