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A42MX36-VQ208A Datasheet(PDF) 7 Page - Actel Corporation |
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A42MX36-VQ208A Datasheet(HTML) 7 Page - Actel Corporation |
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7 / 78 page  40MX and 42MX Automotive FPGA Families v3.1 1-3 Routing Structure The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be continuous or split into segments. Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Horizontal Routing Horizontal routing tracks span the whole row length or are divided into multiple segments and are located in between the rows of modules. Any segment that spans more than one-third of the row length is considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-dedicated tracks are used for signal nets. Vertical Routing Another set of routing tracks run vertically through the module. There are three types of vertical tracks: input, output, and long. Long tracks span the column length of the module, and can be divided into multiple segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 1-6. Antifuse Structures An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. There are no pre-existing connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For instance, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Figure 1-5 • A42MX36 Dual-Port SRAM Block SRAM Module 32 x 8 or 64 x 4 (256 Bits) Read Port Logic Write Port Logic RD[7:0] Routing Tracks Latches Read Logic [5:0] RDAD[5:0] REN RCLK Latches WD[7:0] Latches WRAD[5:0] Write Logic MODE BLKEN WEN WCLK [5:0] [7:0] Figure 1-6 • MX Routing Structure Segmented Horizontal Routing Logic Modules Antifuses Vertical Routing Tracks |
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