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A500K130-BG208 Datasheet(PDF) 10 Page - Actel Corporation |
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A500K130-BG208 Datasheet(HTML) 10 Page - Actel Corporation |
10 / 72 page Pr oAS I C ® 500K Fa mily 10 Discontinued – v3.0 with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 11 on page 11. The ‘1’s and ‘0’s represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASIC devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device; this speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary scan register chain which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Details on the implementation of boundary-scan testing on ProASIC devices can be found in the Actel application note, Using JTAG Boundary-Scan with ProASIC Devices. Figure 10 • ProASIC JTAG Boundary Scan Test Logic Circuit Device Logic I/O I/O I/O I/O I/O Bypass Register Instruction Register TAP Controller Test Data Registers |
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