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A14V60AA-3VQ208C Datasheet(PDF) 7 Page - Actel Corporation |
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A14V60AA-3VQ208C Datasheet(HTML) 7 Page - Actel Corporation |
7 / 68 page 1-181 Accelerator Series FPGAs – ACT ™ 3 Family Architecture This section of the data sheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The on-chip circuitry required to program the devices is not covered. Topology The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array itself consists of alternating rows of modules and channels. The logic modules and channels are in the center of the array; the I/O modules are located along the array periphery. A simplified floor plan is depicted in Figure 1. Logic Modules ACT 3 logic modules are enhanced versions of the 1200XL family logic modules. As in the 1200XL family, there are two types of modules: C-modules and S-modules. The C-module is functionally equivalent to the 1200XL C-module and implements high fanin combinatorial macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The S-module is designed to implement high-speed sequential functions within a single module. S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be implemented without additional propagation delay. It is available for use as the DFM8A/B and DLM8A/B hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are arranged in alternating patterns and make up the bulk of the array. This arrangement allows the placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module implements the following function: Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11 where: S0 = A0 * B0 and S1 = A1 + B1 Figure 1 • Generalized Floor Plan of ACT 3 Device IO IO IO IO IO IO C S C S S IO IO C C S C S S IO IO C C S C S S IO IO C BIO IO IO IO IO IO IO IO BIN S C C S S IO IO BIN S C C S S IO IO BIN S C C S S IO IO IO CLKM IO IO IO IO IO IO IO BIN S C IO C S S C S C S S IO IO C An Array with n rows and m columns Top I/Os Bottom I/Os Left I/Os Right I/Os Rows n+1 n n–1 • • • 2 1 0 Channels n+1 n n–1 • • • 2 1 0 n+2 0 1 2 3 4 5 c–1 c c+1 m m+1 m+2 m+3 Columns |
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