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AGL400V2-CS144ES Datasheet(PDF) 1 Page - Actel Corporation |
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AGL400V2-CS144ES Datasheet(HTML) 1 Page - Actel Corporation |
1 / 212 page December 2008 I © 2008 Actel Corporation IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • 1.2 V to 1.5 V Core Voltage Support for Low Power • Supports Single-Voltage System Operation • 5 µW Power Consumption in Flash*Freeze Mode • Low-Power Active FPGA Operation • Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode High Capacity • 15 k to 1 Million System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal, Flash-Based CMOS Process • Live-at-Power-Up (LAPU) Level 0 Support • Single-Chip Solution • Retains Programmed Design When Powered Off In-System Programming (ISP) and Security • Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO® devices) via JTAG (IEEE 1532–compliant)1 •FlashLock® to Secure FPGA Contents High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure Advanced I/O • 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above) • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X1, and LVCMOS 2.5 V / 5.0 V Input1 • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M- LVDS (AGL250 and above) • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os‡ • Programmable Output Slew Rate1 and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the IGLOO Family Clock Conditioning Circuit (CCC) and PLL1 • Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit 1 RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations) • True Dual-Port SRAM (except ×18) 1 ARM Processor Support in IGLOO FPGAs • M1 IGLOO Devices—Cortex™-M1 Soft Processor Available with or without Debug ® 1 AGL015 and AGL030 devices do not support this feature. ‡ Supported only by AGL015 and AGL030 devices. IGLOO Product Family IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 ARM-Enabled IGLOO Devices M1AGL250 M1AGL400 M1AGL600 M1AGL1000 System Gates 15 k 30 k 60 k 125 k 250 k 400 k 600 k 1 M Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – – VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576 Flash*Freeze Mode (typical, µW) 5 5 10 16 24 32 36 53 RAM kbits (1,024 bits) – – 18 36 36 54 108 144 4,608-Bit Blocks –– 4 8 8 12 24 32 FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k Secure (AES) ISP 1 – – Yes Yes Yes Yes Yes Yes Integrated PLL in CCCs 2 –– 1 1 1 1 1 1 VersaNet Globals 3 6 6 18 18 18 18 18 18 I/O Banks 22 2 2 4 4 4 4 Maximum User I/Os 49 81 96 133 143 194 235 300 Package Pins UC/CS QFN VQFP FBGA QN68 UC81/CS81 QN48, QN68, QN132 VQ100 CS121 QN132 VQ100 FG144 5 CS196 QN132 VQ100 FG144 CS196 4 QN132 4,5 VQ100 FG144 CS196 FG144, FG256, FG484 CS281 FG144, FG256, FG484 CS281 FG144, FG256, FG484 Notes: 1. AES is not available for ARM-enabled IGLOO devices. 2. AGL060 in CS121 does not support the PLL. 3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above. 4. The M1AGL250 device does not support this package. 5. Device/package support TBD 6. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology handbook. v1.3 |
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