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LTC1266IS-3.3 Datasheet(PDF) 8 Page - Linear Technology |
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LTC1266IS-3.3 Datasheet(HTML) 8 Page - Linear Technology |
8 / 20 page 8 LTC1266 LTC1266-3.3/LTC1266-5 When the voltage on the timing capacitor has discharged past VTH1, comparator T trips, setting the flip-flop. This causes the bottom-side output to switch off and the topside output to switch on (ground for P-channel and Power VIN for N-channel). The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage (Pin 7) to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the topside MOSFET is held off by comparator V and the timing capacitor continues to discharge below VTH1. When the timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal sleep line to go low and the bottom-side MOSFET to turn off. The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode, a majority of the circuitry is turned off, dropping the quiescent current from 2.1mA to 170 µA. The load current is now being supplied from the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the topside MOSFET is again turned on and this process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset VOS is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. One of the three basic LTC1266 application circuits is shown in Figure 1. This circuit uses an N-channel topside driver and a single supply. The other two circuit configurations (see Typical Applications) use an N-channel topside driver and dual supply, and a P-channel topside driver. Selections of other external components are driven by the load requirement and are the same for all three circuit configurations. The first step is the selection of RSENSE. Once RSENSE is known, CT and L can be chosen. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected and the loop is compensated. Using an N-channel topside switch, input voltages are limited to a maximum of about 15V. With a P-channel, the input voltage may be as high as 20V. To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the bottom-side drive output can turn on, the topside output must be off. Likewise, the topside output is prevented from turning on while the bottom-side drive output is still on. The LTC1266 has two select pins which provide the user with choice of topside switch and with the option of inhibiting Burst Mode operation. The phase select pin allows the user to choose whether the topside MOSFET is a P-channel or an N-channel. The phase select pin does two things: sets the proper phase of the drive signal (ON = Power VIN for N-channel and ON = 0V for P-channel) and also sets an upper limit for the on-time (60 µs) when set to the N-channel. The on-time limit ensures proper start-up when used in a single supply bootstrap circuit configuration (see Applications Information). In P-channel mode there is no on-time limit and thus, in dropout, the P-channel MOSFET is turned on continuously (100% duty cycle). The Burst Mode operation inhibit (BINH, Pin 4) allows the Burst Mode operation to be disabled by applying a CMOS logic high to this pin. With Burst Mode operation disabled, the LTC1266 will remain in continuous mode down to zero load. Burst Mode operation is disabled by allowing the lower current threshold limit to go below zero so that the voltage comparator will never trip. The voltage comparator trip point is also raised up so that it will not be tripped by transients. It is still active to provide a voltage clamp to prevent the output from overshooting. OPERATIO APPLICATIO S I FOR ATIO |
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