7

LTC1266

LTC1266-3.3/LTC1266-5

Pin 10 Connection Shown for LTC1266-3.3 and LTC1266-5; Changes Create LTC1266

+

–

16

4

1

3

15 PGND

BDRIVE

TDRIVE

PINV

BINH

2

R

S

Q

C

7

13k

PINV

1.265V

11

5

REFERENCE

SHDN

V

G

9

10

ADJUSTABLE

VERSION

100k

5pF

T

–

+

S

SLEEP

12

SIGNAL

GROUND

6

OFF-TIME

CONTROL

MAX

ON-TIME

CONTROL

8

1266 FD

ENABLE

14

LB

13

1.25V

REFERENCE

The LTC1266 series uses a current mode, constant off-

time architecture to synchronously switch an external pair

of power MOSFETs. Operating frequency is set by an

external capacitor at the timing capacitor Pin 6.

The output voltage is sensed by an internal voltage divider

A voltage comparator V, and a gain block G, compare the

divided output voltage with a reference voltage of 1.265V.

To optimize efficiency, the LTC1266 automatically switches

between two modes of operation, burst and continuous.

The voltage comparator is the primary control element

when the device is in Burst Modeoperation, while the gain

block controls the output voltage in continuous mode.

During the switch ON cycle in continuous mode, current

comparator C monitors the voltage between Pins 8 and 9

connected across an external shunt in series with the

inductor. When the voltage across the shunt reaches its

threshold value, the topside driver output is switched to

ground for N-channel). The timing capacitor connected to

Pin 6 is now allowed to discharge at a rate determined by

the off-time controller. The discharge current is made

proportional to the output voltage (measured by Pin 8) to

model the inductor current, which decays at a rate which

is also proportional to the output voltage. While the timing

capacitor is discharging, the bottom-side drive output is

N-channel MOSFET.

FU CTIO AL DIAGRA

OPERATIO