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ADSP-21061KS-200 Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-21061KS-200 Datasheet(HTML) 5 Page - Analog Devices |
5 / 47 page ADSP-21061/ADSP-21061L –5– REV. B Off-Chip Memory and Peripherals Interface The ADSP-21061’s external port provides the processor’s inter- face to off-chip memory and peripherals. The 4-gigaword off- chip address space is included in the ADSP-21061’s unified address space. The separate on-chip buses—for program memory, data memory and I/O—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. The on-chip Super Harvard Architecture provides three-bus performance, while the off-chip unified address space gives flexibility to the designer. Addressing of external memory devices is facilitated by on-chip decoding of high order address lines to generate memory bank select signals. Separate control lines are also generated for sim- plified addressing of page-mode DRAM. The ADSP-21061 provides programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripher- als with variable access, hold and disable time requirements. Host Processor Interface The ADSP-21061’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the processor are supported. The host interface is accessed through the ADSP-21061’s exter- nal port and is memory-mapped into the unified address space. Two channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-21061’s external bus with the host bus request ( HBR), host bus grant (HBG) and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-21061, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands. DMA Controller The ADSP-21061’s on-chip DMA controller allows zero- overhead, nonintrusive data transfers without processor inter- vention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21061’s internal memory and either external memory, external peripherals, or a host processor. DMA transfers can also occur between the ADSP-21061’s internal memory and its serial ports. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32- or 48-bit words is performed during DMA transfers. Six channels of DMA are available on the ADSP-21061—four via the serial ports, and two via the processor’s external port (for either host processor, other ADSP-21061s, memory or I/O transfers). Programs can be downloaded to the ADSP-21061 using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines ( DMAR 1-2, DMAG1-2). Other DMA features include interrupt generation upon completion of DMA transfers and DMA chain- ing for automatic linked DMA transfers. Serial Ports The ADSP-21061 features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at the full clock rate of the processor, providing each with a maxi- mum data rate of 40 Mbit/s. Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via DMA. Each of the serial ports offers TDM multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from three bits to 32 bits. They offer selectable synchronization and trans- mit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated. The serial ports also include keyword and keymask features to enhance interprocessor communication. Multiprocessing The ADSP-21061 offers powerful features tailored to multipro- cessing DSP systems. The unified address space allows direct interprocessor accesses of each ADSP-21061’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21061s and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify- write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for inter- processor data transfer is 500 Mbytes/sec over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21061s and can be used to implement reflective semaphores. Program Booting The internal memory of the ADSP-21061 can be booted at system power-up from either an 8-bit EPROM or a host proces- sor. Selection of the boot source is controlled by the BMS (Boot Memory Select), EBOOT (EPROM Boot), and LBOOT (Host Boot) pins. 32-bit and 16-bit host processors can be used for booting. See the BMS pin in the Pin Function Descriptions section of this data sheet. |
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