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ADSP-21061LKB-160 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-21061LKB-160 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 47 page  –8– ADSP-21061/ADSP-21061L REV. B Porting Code from ADSP-21060 or ADSP-21062 to the ADSP-21061 The ADSP-21061 is pin compatible with the ADSP-21060/ ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins that correspond to the Link Port pins of the ADSP-21060/ ADSP-21062 are no-connects. The ADSP-21061 is object code compatible with the ADSP- 21060/ADSP-21062 except for the following functional changes: The ADSP-21061 memory is organized into two blocks with eight columns that are 4K deep per block. The ADSP-21060/ADSP-21062 memory has 16 columns per block. Link port functions are not available. Handshake external port DMA pins DMAR2 and DMAG2 are assigned to external port DMA Channel 6 instead of Channel 8. 2-D DMA capability of the SPORT is not available. The modify registers in SPORT DMA are not programmable. On the ADSP-21061, Block 0 starts at the beginning of internal memory, normal word address 0x0002 0000. Block 1 starts at the end of Block 0, with contiguous addresses. The remaining addresses in internal memory are divided into blocks that alias into Block 1. This allows any code or data stored in Block 1 on the ADSP-21062 to retain the same addresses on the ADSP- 21061—these addresses will alias into the actual Block 1 of each processor. If you develop your application using the ADSP-21062, but will migrate to the ADSP-21061, use only the first eight columns of each memory bank. Limit your application to 8K of instructions or up to 16K of data in each bank of the ADSP-21062, or any combinations of instructions or data that does not exceed the memory bank. DEVELOPMENT TOOLS The ADSP-21061 is supported with a complete set of software and hardware development tools, including an EZ-ICE In- Circuit Emulator, EZ-Kit Lite, and development software. The SHARC EZ-Kit Lite (ADDS-2106x-EZ-Lite) is a complete low cost package for DSP evaluation and prototyping. The EZ-Kit Lite contains an evaluation board with an ADSP-21061 (5 V) processor and provides a serial connection to your PC. The EZ- Kit Lite also includes an optimizing compiler, assembler, in- struction level simulator, run-time libraries, diagnostic utilities and a complete set of example programs. CBUG and SHARCPAC are trademarks of Analog Devices, Inc. The same EZ-ICE hardware can be used for the ADSP-21060/ ADSP-21062, to fully emulate the ADSP-21061, with the excep- tion of displaying and modifying the two new SPORTS registers. The emulator will not display these two registers, but your code can use them. Analog Devices ADSP-21000 Family Development Software includes an easy to use Assembler based on an algebraic syntax, Assembly Library/Librarian, Linker, instruction-level Simulator, an ANSI C optimizing Compiler, the CBUG™ C Source— Level Debugger and a C Runtime Library including DSP and mathematical functions. The Optimizing Compiler includes Numerical C extensions based on the work of the ANSI Nu- merical C Extensions Group. Numerical C provides extensions to the C language for array selections, vector math operations, complex data types, circular pointers and variably dimensioned arrays. The ADSP-21000 Family Development Software is available for both the PC and Sun platforms. The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-21061 processor to monitor and control the target board processor during emulation. The EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter- face—the emulator does not affect target system loading or timing. Further details and ordering information are available in the ADSP-21000 Family Hardware and Software Development Tools data sheet (ADDS-210xx-TOOLS). This data sheet can be requested from any Analog Devices sales office or distributor. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard- ware tools include SHARC PC plug-in cards multiprocessor SHARC VME boards, and daughter and modules with multiple SHARCs and additional memory. These modules are based on the SHARCPAC™ module specification. Third Party software tools include an Ada compiler, DSP libraries, operating systems and block diagram design tools. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21061 architecture and functionality. For detailed information on the ADSP-21000 Family core architecture and instruction set, refer to the ADSP-2106x SHARC User’s Manual, Second Edition. |
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