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AK4421ET Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AK4421ET Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
11 / 19 page ![]() [AK4421] MS0945-E-01 2008/08 - 11 - ■ Zero detect function When the input data for both channels are continuously zero for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF pin immediately returns to “L” if the input data for both channels are not zero (Figure 5). ■ Analog output block The internal negative power supply generation circuit (Figure 5) provides a negative power supply for the internal 2Vrms amplifier. It allows the AK4421 to output an audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative power generation circuit (Figure 5) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by clocks generated from MCLK. When MCLK stops, the AK4421 is placed in reset mode automatically and the analog outputs settle to VSS (0V, typ). CVDD Charge Pump CP CN VSS2 VEE 1uF 1uF Negative Power AK4421 (+) Cb Ca (+) Figure 5. Negative Power Generation Circuit AOUTR AK4421 (AOUTL) 0V 2Vrms Figure 6. Audio Signal Output |
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