www.rhombus-ind.com

TEL: (714) 898-0960

sales@rhombus-ind.com

FAX: (714) 896-0971

6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH

)RU RWKHU YDOXHV&XVWRP 'HVLJQV FRQWDFW IDFWRU\

UKRPEXV LQGXVWULHV LQF

PECL3-H 2001-02

27

V

........................................... -5.20

± 0.25VDC

I

EE

Supply Current ............................................... 60 mA typical

Logic “1” Input:

V

I

I

-11mA typ.

Logic “0” Input:

V

I

0.5

µA min.

I

V

OH

Logic “1” Voltage Out ......................................... -.96V min.

V

OL

Logic “0” Voltage Out ....................................... -1.65V max.

P

WI

Input Pulse Width .......................... 40% of Max. Delay min.

V

........................................... -5.20

± 0.25VDC

I

EE

Supply Current ............................................... 75 mA typical

Logic “1” Input:

V

I

I

-11mA typ.

Logic “0” Input:

V

I

0.7

µA min.

I

V

OH

Logic “1” Voltage Out ......................................... -.96V min.

V

OL

Logic “0” Voltage Out ....................................... -1.65V max.

P

WI

Input Pulse Width .......................... 40% of Max. Delay min.

* Refer to Input (Pin 6) Loading note above.

.100

(2.54)

TYP.

.045

(1.14)

TYP.

.020

(0.51)

TYP.

.815

(20.70)

.070

(1.78)

.590

(14.99)

.895

(22.73)

MAX.

MAX.

.010

(0.25)

TYP.

.295

(7.49)

MAX.

.010

(0.25)

16-Pin SMD Pkg. Unused leads are NOT removed.

To Specify SMD Package, Add "H" Suffix to P/N

Examples: PECL3-1.25H, 3PECLH-2H

Dimensions in Inches (mm)

ECL 3-Bit

Schematic

1

6

7

Vcc

Vcc

OUT

28

16

15

10

9

E

IN

P1

Vee

P3

P2

3-Bit Programmable

Delay Line

Output

Buffer

MAX.

.260

(6.60)

TYP.

.810

(20.57)

.300

(7.62)

MAX.

.100

(2.54)

TYP.

.050

(1.27)

TYP.

.020

(0.51)

TYP.

.120

(3.05)

MIN.

.300

(7.62)

.400

(10.16)

MAX.

.010

(0.25)

TYP.

INPUT LOADING: Input, Pin 6, internally connected to eight ECL

gate inputs terminated by Thevenin equivalent of 100 Ohms to -2V.

** INITIAL DELAY & CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays Referenced to Initial Delay, Setting "000."

For example, the setting "111" delay of PECL3-2 is 14.0

± 0.8 ns ref. to "000," and 17.0 ± 1.3 ns referenced to the input,

and the setting "111" delay of 3PECLH-2 is 14.0

± 0.8 ns ref. to "000," and 15.5 ± 1.3 ns referenced to the input.

_

ENABLE input E , Pin 2, is active low.

Output is disabled (low) when Pin 2 is logic high.

3Bit 10K ECL

DIP Part Number

3-Bit 10KH ECL

DIP Part Number

Delay per

Step (ns)

Error ref.

to "000"

(ns)

Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)

"000"=3±0.5ns **

"000"=1.5±.5ns **

000

001

010

011

100

101

110

111

PECL3-0.5

3PECLH-0.5

0.5 ± .25

± .30

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

PECL3-0.75

3PECLH0.75

0.75 ± .3

± .50

0.0

0.75

1.50

2.25

3.00

3.75

4.50

5.25

PECL3-1

3PECLH-1

1.0 ± .4

± .50

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

PECL3-1.25

3PECLH1.25

1.25 ± .5

± .70

0.0

1.25

2.50

3.75

5.00

6.25

7.50

8.75

PECL3-1.5

3PECLH-1.5

1.5 ± .5

± .70

0.0

1.5

3.0

4.5

6.0

7.5

9.0

10.5

PECL3-2

3PECLH-2

2.0 ± .7

± .80

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

PECL3-2.5

3PECLH-2.5

2.5 ± .7

± .90

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

PECL3-3

3PECLH-3

3.0 ± .7

± 1.0

0.0

3.0

6.0

9.0

12.0

15.0

18.0

21.0

PECL3-5

3PECLH-5

5.0 ± 1.0

± 1.5

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

PECL3-10

3PECLH-10

10.0 ± 1.5

± 3.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

3-Bit Programmable Delay Modules

PECL3 Series 10K ECL Logic

Available in Surface Mount