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BQ2058CSN-C5TR Datasheet(PDF) 6 Page - Texas Instruments |
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BQ2058CSN-C5TR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 14 page The FETs in the charge/discharge path controlled by the CHG and DSG pins affect the overcurrent level. The on-resistance of these FETs need to be taken into ac- count when determining overcurrent levels. CHG and DSG States The CHG and DSG output truth table is shown below. The polarities of CHG and DSG are mask programmable at Unitrode. Push-pull vs. open-drain configuration is also mask-configurable at Unitrode. Please contact Unitrode for availability of these variations. Number of Cells The user must configure the bq2058 for three- or four- series cell operation. For a three-cell pack, NSEL should be tied directly to VSS. For a four-cell pack, NSEL should be connected directly to VCC. Pack Disable Input–CTL The CTL pin is used to electrically disconnect the bat- tery from the pack terminals through an externally sup- plied signal. When CTL is taken high, CHG and DSG are driven high. Any load on the pack terminals will be interpreted as an overcurrent condition by the bq2058 with the overcurrent delay timer held in reset. When the CTL pin is driven low, the overcurrent delay timer is allowed to start. If the programmed delay (tOCD)istoo short, the overcurrent recovery circuit, if implemented, will be unable to correct the overcurrent situation prior to the delay time-out. It is recommended that a delay time of greater than 10ms (COCD ≥ 0.01µF) be used if the CTL pin function is used. Important note: If CTL floats, it is internally pulled high making both DSG and CHG inactive, thus disabling the pack. If CTL is not used, it should be tied to VSS. The polarity of CTL is mask programmable at Unitrode. Please contact Unitrode for other polarity options. Protection Delay Timers The delay time between the detection of an overcurrent, overvoltage, or undervoltage condition and the deactivation of the CHG and/or DSG outputs is user-configurable by the selection of capacitor values between VCC and OCD, OVD, and UVD pins (respectively). See Table 3 below. The fault condition must persist through the entire de- lay period, or the bq2058 may not deactivate either FET control output. Figure 3 shows a step-by-step event cycle for the bq2058. 6 Table 3. Protection Delay Timers Protection Feature Delay Period Capacitor from VCC to: Typical Tolerance Capacitor Time Overcurrent tOCD OCD 0.010 µF 12ms ±40% Overvoltage tOVD OVD 0.100 µF 950ms ±40% Undervoltage tUVD UVD 0.100 µF 950ms ±40% Notes: 1. The delay time versus capacitance can be approximated by the following equations:. For tOCD:t(s) ≈ 1.2 ∗ C(µf), where C ≥ 0.001µF For tOVD, tUVD:t(s) ≈ 9.5 ∗ C(µf), where C ≥ 0.01µF 2. Overvoltage and undervoltage conditions are sampled by the bq2058. The delay in Table 2 is in addition to the time required for the bq2058 to detect the violation, which may vary from 0 to 160 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously monitored and is subject to a delay of approximately 1.5ms. bq2058 Condition CHG pin DSG pin Normal operation Low Low Overvoltage High Low Undervoltage Low High Overcurrent Low High Floating battery input High Indeterminate CTL = high High High Number of Series Cells NSEL 3-cell Tied to VSS 4-cell Tied to VCC |
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