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BQ2945SN-C409TR Datasheet(PDF) 2 Page - Texas Instruments |
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BQ2945SN-C409TR Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 32 page  Pin Descriptions VCC Supply voltage input LED1– LED5 LED display segment outputs Each output may drive an external LED. ESCL Serial memory clock Output used to clock the data transfer be- tween the bq2945 and the external non- volatile configuration memory. ESDA Serial memory data and address Bidirectional pin used to transfer ad- dress and data to and from the bq2945 and the external nonvolitile configura- tion memory. CP1– CP2 Control pins 1 and 2 These open-drain outputs can be con- trolled by an SMBus command from the host. CP2 can also act as a digital input. VSS Ground SR Sense resistor input The voltage drop (VSR) across pins SR and VSS is monitored and integrated over time to interpret charge and discharge activity. The SR input is connected to the sense re- sistor and the negative terminal of the battery. VSR <VSS indicates discharge, and VSR >VSS indicates charge. The effective voltage drop, VSRO, as seen by the bq2945 is VSR +VOS. (See Table 3.) DISP Display control input DISP high disables the LED display. DISP floating allows the LED display to be active during charge if the rate is greater than 100mA. DISP low activates the display for 4 seconds. SB Secondary battery input Monitors the pack voltage through a high- impedance resistor divider network. The pack voltage is reported in the SBD register function Voltage (0x09) and is monitored for end-of-discharge voltage and charging volt- age parameters. SMBD SMBus data Open-drain bidirectional pin used to trans- fer address and data to and from the bq2945. SMBC SMBus clock Open-drain bidirectional pin used to clock the data transfer to and from the bq2945. REF Reference output for regulator REF provides a reference output for an op- tional FET-based micro-regulator. VOUT Supply output Supplies power to the external EEPROM configuration memory. 2 bq2945 |
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