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BQ3285ECSSTR Datasheet(PDF) 6 Page - Texas Instruments |
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BQ3285ECSSTR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 26 page  32kHz Output The bq3285EC/LC provides for a 32.768kHz output. For the bq3285EC, the output is always active whenever VCC is valid (VPFD +tCSR). The bq3285EC output is not af- fected by the bit settings in Register A. Time-keeping aspects, however, still require setting OS0-OS2. The bq3285LC output is active when the oscillator is turned on by setting the OSC0-OSC2 bits in Register A. Interrupts The bq3285EC/LC allows three individually selected in- terrupt events to generate an interrupt request. These three interrupt events are: n The periodic interrupt, programmable to occur once every 122 µs to 500ms. n The alarm interrupt, programmable to occur once per second to once per day, is active in battery-backup mode, providing a “wake-up” feature. n The update-ended interrupt, which occurs at the end of each update cycle. Each of the three interrupt events is enabled by an indi- vidual interrupt-enable bit in register B. When an event occurs, its event flag bit in register C is set. If the corre- sponding event enable bit is also set, then an interrupt request is generated. The interrupt request flag bit (INTF) of register C is set with every interrupt request. Reading register C clears all flag bits, including INTF, and makes INT high-impedance. Two methods can be used to process bq3285EC/LC in- terrupt events: n Enable interrupt events and use the interrupt request output to invoke an interrupt service routine. n Do not enable the interrupts and use a polling routine to periodically check the status of the flag bits. The individual interrupt sources are described in detail in the following sections. 6 bq3285EC/LC Register A Bits Periodic Interrupt OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0 Period Units 010000 0 None 010000 1 3.90625 ms 010001 0 7.8125 ms 010001 1 122.070 µs 010010 0 244.141 µs 010010 1 488.281 µs 010011 0 976.5625 µs 010011 1 1.95315 ms 010100 0 3.90625 ms 010100 1 7.8125 ms 010101 0 15.625 ms 010101 1 31.25 ms 010110 0 62.5 ms 010110 1 125 ms 010111 0 250 ms 010111 1 500 ms 011 X X X X same as above defined by RS3–RS0 Table 3. Periodic Interrupt Rate July 1996 |
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