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BQ3285ESS- Datasheet(PDF) 10 Page - Texas Instruments |
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BQ3285ESS- Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 29 page  UTI - Update Transfer Inhibit This bit inhibits the transfer of RTC bytes to the user buffer: 1 = Inhibits transfer and clears UIE 0 = Allows transfer Register C Register C is the read-only event status register. Bits 0, 1, 3 - Unused Bits These bits are always set to 0. 32KE - 32kHz Enable Output This bit may be set to a 1 only when the OSC2–OSC0 bits in register A are set to 011. Setting OSC2–OSC0 to anything other than 011 clears this bit. If SQWE in reg- ister B and 32KE are set, a 32.768kHz waveform is out- put on the square wave pin. UF - Update Event Flag This bit is set toa1attheendofthe update cycle. Reading register C clears this bit. AF - Alarm Event Flag This bit is set to a 1 when an alarm event occurs. Read- ing register C clears this bit. PF - Periodic Event Flag This bit is set to a 1 every tPI time, where tPI is the time period selected by the settings of RS0–RS3 in register A. Reading register C clears this bit. INTF - Interrupt Request Flag This flag is set to a 1 when any of the following is true: AIE = 1 and AF = 1 PIE = 1 and PF = 1 UIE = 1 and UF = 1 Reading register C clears this bit. Register D Register D is the read-only data integrity status register. Bits 0–6 - Unused Bits These bits are always set to 0. VRT - Valid RAM and Time 1 = Valid backup energy source 0 = Backup energy source is depleted When the backup energy source is depleted (VRT = 0), data integrity of the RTC and storage registers is not guaranteed. 10 Register C Bits 7654 3 210 INTF PF AF UF 0 32KE 0 0 7654 3 210 ---- 0 - 0 0 7654 3 210 --- UF - --- 7654 3 210 -- AF - - --- 7654 3 210 -PF- - - - - - 7654 3 210 INTF - - - - - - - Register D Bits 7654 3 210 VRT 000 0 000 7654 3 210 - 000 0 000 7654 3 210 UTI --- - --- 7654 3 210 VRT --- - --- 7654 3 210 ---- - 32KE - - bq3285E/L |
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