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BQ4017MC-70 Datasheet(PDF) 1 Page - Texas Instruments |
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BQ4017MC-70 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 12 page  Features ➤ Data retention in the absence of power ➤ Automatic write-protection dur- ing power-up/power-down cycles ➤ Conventional SRAM operation; unlimited write cycles ➤ 5-year minimum data retention in absence of power ➤ Battery internally isolated until power is applied General Description The CMOS bq4017 is a nonvolatile 16,777,216-bit static RAM organized as 2,097,152 words by 8 bits. The integral control circuitry and lith- ium energy source provide reliable nonvolatility coupled with the un- limited write cycles of standard SRAM. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC falls out of tolerance, the SRAM is unconditionally write-protected to prevent an inadvertent write opera- tion. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The bq4017 uses extremely low standby current CMOS SRAMs, cou- pled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EE- PROM. The bq4017 has the same interface as industry-standard SRAMs and requires no external circuitry. 1 Selection Guide Part Number Maximum Access Time (ns) Negative Supply Tolerance Part Number Maximum Access Time (ns) Negative Supply Tolerance bq4017MC -70 70 -5% bq4017YMC -70 70 -10% 1 PN401701.eps 36-Pin DIP Module 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 VSS DQ0 VCC A19 NC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ5 DQ4 DQ3 DQ6 Pin Names A0–A20 Address inputs DQ0–DQ7 Data input/output CE Chip enable input OE Output enable input WE Write enable input VCC Supply voltage input VSS Ground NC No connect Block Diagram bq4017/bq4017Y 5/95 Pin Connections 2048Kx8 Nonvolatile SRAM |
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