 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
BQ4832Y Datasheet(PDF) 3 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
BQ4832Y Datasheet(HTML) 3 Page - Texas Instruments |
|
|
3 / 18 page  Address Map The bq4832Y provides 16 bytes of clock and control status registers and 32,752 bytes of storage RAM. Figure 2 illustrates the address map for the bq4832Y. Table 1 is a map of the bq4832Y registers, and Table 2 describes the register bits. Memory Interface Read Mode The bq4832Y is in read mode whenever OE (output en- able) is low and CE (chip enable) is low. The device ar- chitecture allows ripple-through access of data from eight of 262,144 locations in the static storage array. Thus, the unique address specified by the 15 address in- puts defines which one of the 32,768 bytes of data is to be accessed. Valid data is available at the data I/O pins within tAA (address access time) after the last address input signal is stable, providing that the CE and OE (output enable) access times are also satisfied. If the CE and OE access times are not met, valid data is available after the latter of chip enable access time (tACE) or out- put enable access time (tOE). CE and OE control the state of the eight three-state data I/O signals. If the outputs are activated before tAA, the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CE and OE remain low, output data remains valid for tOH (output data hold time), but goes indeterminate until the next address access. Write Mode The bq4832Y is in write mode whenever WE and CE are active. The start of a write is referenced from the latter-occurring falling edge of WE or CE. A write is ter- minated by the earlier rising edge of WE or CE. The ad- dresses must be held valid throughout the cycle. CE or WE must return high for a minimum of tWR2 from CE or tWR1 from WE prior to the initiation of another read or write cycle. Data-in must be valid tDW prior to the end of write and remain valid for tDH1 or tDH2 afterward. OE should be kept high during write cycles to avoid bus contention; al- though, if the output bus has been activated by a low on CE and OE, a low on WE disables the outputs tWZ after WE falls. 3 FG483201.eps Clock and Control Status Registers 7FFF 7FF0 7FEF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Year Month Date Days Hours Minutes Seconds Control Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Tenths/ Hundredths Flags 7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8 7FF7 7FF6 7FF5 7FF4 7FF3 7FF2 7FF1 7FF0 Storage RAM 16 Bytes 32,752 Bytes 0000 Figure 2. Address Map Sept. 1996 C bq4832Y |
Similar Part No. - BQ4832Y |
|
Similar Description - BQ4832Y |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
