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BQ4852YMC-85 Datasheet(PDF) 4 Page - Texas Instruments |
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BQ4852YMC-85 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 16 page  place. When VCC drops below VSO, the control circuit switches power to the internal energy source, which pre- serves data. The internal coin cell maintains data in the bq4852Y af- ter the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is discon- nected, and the power supply is switched to external VCC. Write-protection continues for tCER after VCC reaches VPFD to allow for processor stabilization. After tCER, normal RAM op- eration can resume. Clock Interface Reading the Clock The interface to the clock and control registers of the bq4852Y is the same as that for the general-purpose storage memory. Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real time counters. To prevent reading data in transition, updates to the bq4852Y clock regis- ters should be halted. Updating is halted by setting the read bit D6 of the control register to 1. As long as the read bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is re- trieved by reading the appropriate clock memory loca- tions, the read bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the read bit, reading the clock locations has no effect on clock ac- curacy. Once the read bit is reset to 0, within one second the internal registers update the user-accessible regis- ters with the correct time. A halt command issued dur- ing a clock update allows the update to occur before freezing the data. Setting the Clock Bit D7 of the control register is the write bit. Like the read bit, the write bit when set to a 1 halts updates to the clock/calendar memory locations. Once frozen, the locations can be written with the desired information in 24-hour BCD format. Resetting the write bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible regis- ters to resume within one second. Use the write bit, D7, only when updating the time registers (7FFFF–7FFF9). 4 Aug. 1996 Address D7 D6 D5 D4 D3 D2 D1 D0 Range (h) Register 7FFFF 10 Years Year 00–99 Year 7FFFF X X X 10 Month Month 01–12 Month 7FFFD X X 10 Date Date 01–31 Date 7FFFC X FTE X X X Day 01–07 Days 7FFFB X X 10 Hours Hours 00–23 Hours 7FFFA X 10 Minutes Minutes 00–59 Minutes 7FFF9 OSC 10 Seconds Seconds 00–59 Seconds 7FFF8 W R S Calibration 00–31 Control 7FFF7 WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0 Watchdog 7FFF6 AIE PWRIE ABE PIE RS3 RS2 RS1 RS0 Interrupts 7FFF5 ALM3 X 10-date alarm Alarm date 01–31 Alarm date 7FFF4 ALM2 X 10-hour alarm Alarm hours 00–23 Alarm hours 7FFF3 ALM1 Alarm 10 minutes Alarm minutes 00–59 Alarm minutes 7FFF2 ALM0 Alarm 10 seconds Alarm seconds 00–59 Alarm seconds 7FFF1 0.1 seconds 0.01 seconds 00–99 0.1/0.01 seconds 7FFF0 WDF AF PWRF BLF PF X X X Flags Notes: X = Unused bits; can be written and read. Clock/Calendar data in 24-hour BCD format. BLF = 1 for low battery. OSC = 1 stops the clock oscillator. Interrupt enables are cleared on power-up. Table 1. bq4842 Clock and Control Register Map bq4852Y |
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