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CD74HCT597E Datasheet(PDF) 1 Page - Texas Instruments |
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CD74HCT597E Datasheet(HTML) 1 Page - Texas Instruments |
1 / 10 page 1 Data sheet acquired from Harris Semiconductor SCHS191 Features • Buffered Inputs • Asynchronous Parallel Load • Typical fMAX = 60MHz at VCC =5V, CL = 15pF, TA =25 oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Description The Harris CD74HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A “low” on the parallel load input (PL) shifts parallel stored data asyn- chronously into the shift register. A “low” master input (MR) clears the shift register. Serial input data can also be synchro- nously shifted through the shift register when PL is high. Pinout CD74HC597, CD74HCT597 (PDIP, SOIC) TOP VIEW Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CD74HC597E -55 to 125 16 Ld PDIP E16.3 CD74HCT597E -55 to 125 16 Ld PDIP E16.3 CD74HC597M -55 to 125 16 Ld SOIC M16.15 CD74HCT597M -55 to 125 16 Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 D1 D2 D3 D4 D5 D6 GND D7 VCC DS PL STCP SHCP MR Q7 D0 January 1998 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 1915.1 CD74HC597, CD74HCT597 High Speed CMOS Logic 8-Bit Shift Register with Input Storage [ /Title (CD74 HC597 , CD74 HCT59 7) /Sub- ject (High Speed CMOS |
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