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EP1C20F400C7ES Datasheet(PDF) 52 Page - Altera Corporation |
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EP1C20F400C7ES Datasheet(HTML) 52 Page - Altera Corporation |
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52 / 106 page  2–46 Altera Corporation Preliminary May 2008 Cyclone Device Handbook, Volume 1 to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output registers. Table 2–9 shows the programmable delays for Cyclone devices. There are two paths in the IOE for a combinatorial input to reach the logic array. Each of the two paths can have a different delay. This allows you adjust delays from the pin to internal LE registers that reside in two different areas of the device. The designer sets the two combinatorial input delays by selecting different delays for two different paths under the Decrease input delay to internal cells logic option in the Quartus II software. When the input signal requires two different delays for the combinatorial input, the input register in the IOE is no longer available. The IOE registers in Cyclone devices share the same source for clear or preset. The designer can program preset or clear for each individual IOE. The designer can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available to the designer for the IOE registers. External RAM Interfacing Cyclone devices support DDR SDRAM and FCRAM interfaces at up to 133 MHz through dedicated circuitry. DDR SDRAM and FCRAM Cyclone devices have dedicated circuitry for interfacing with DDR SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins. However, the configuration input pins in bank 1 must operate at 2.5 V because the SSTL-2 VCCIO level is 2.5 V. Additionally, the configuration Table 2–9. Cyclone Programmable Delay Chain Programmable Delays Quartus II Logic Option Input pin to logic array delay Decrease input delay to internal cells Input pin to input register delay Decrease input delay to input registers Output pin delay Increase delay to output pin |
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