 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EPM570GF100A Datasheet(PDF) 24 Page - Altera Corporation |
|
||||||||||||||||||||||||||||||
EPM570GF100A Datasheet(HTML) 24 Page - Altera Corporation |
|
|
24 / 86 page  2–16 Chapter 2: MAX II Architecture Global Signals MAX II Device Handbook © October 2008 Altera Corporation The UFM block communicates with the logic array similar to LAB-to-LAB interfaces. The UFM block connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. This block also has DirectLink interconnects for fast connections to and from a neighboring LAB. For more information about the UFM interface to the logic array, see “User Flash Memory Block” on page 2–18. Table 2–2 shows the MAX II device routing scheme. Global Signals Each MAX II device has four dual-purpose dedicated clock pins (GCLK[3..0], two pins on the left side and two pins on the right side) that drive the global clock network for clocking, as shown in Figure 2–13. These four pins can also be used as general- purpose I/O if they are not used to drive the global clock network. The four global clock lines in the global clock network drive throughout the entire device. The global clock network can provide clocks for all resources within the device including LEs, LAB local interconnect, IOEs, and the UFM block. The global clock lines can also be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, or protocol control signals such as TRDY and IRDY for PCI. Internal logic can drive the global clock network for internally-generated global clocks and control signals. Figure 2–13 shows the various sources that drive the global clock network. Table 2–2. MAX II Device Routing Scheme Source Destination LUT Chain Register Chain Local (1) DirectLink (1) R4 (1) C4 (1) LE UFM Block Column IOE Row IOE Fast I/O (1) LUT Chain — — — — — — v —— — — Register Chain — — — — — — v —— — — Local Interconnect —— — — — — vv v v — DirectLink Interconnect —— v —— — — — — — — R4 Interconnect — — v — vv —— — — — C4 Interconnect — — v — vv —— — — — LE vv v v v v —— vv v UFM Block — — vv v v —— — — — Column IOE — — — — — v —— — — — Row IOE — — — vv v —— — — — Note to Table 2–2: (1) These categories are interconnects. |
Similar Part No. - EPM570GF100A |
|
Similar Description - EPM570GF100A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
