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SN54ABT646 Datasheet(HTML) 1 Page - Texas Instruments

Part No. SN54ABT646
Description  OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN54ABT646 Datasheet(HTML) 1 Page - Texas Instruments

 
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SN54ABT646 . . . JT PACKAGE
SN74ABT646 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
5
6
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9
10
11
25
24
23
22
21
20
19
43
2
128
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
SN54ABT646 . . . FK PACKAGE
(TOP VIEW)
17 18
27 26
NC – No internal connection
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
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SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
Copyright
© 1994, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical V
OLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA I
OH,
64-mA IOL)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
description
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the
′ABT646.
Output-enable (OE) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT646 is characterized for operation over the full military temperature range of – 55
°C to 125°C. The
SN74ABT646 is characterized for operation from – 40
°C to 85°C.
EPIC-
ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.


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