SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A

SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D – AUGUST 1993 – REVISED JULY 1996

7

POST OFFICE BOX 655303

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard

1149.1-1990. All test instructions, test data, and test control signals are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, TCK and TMS. The function of the TAP controller is to

extract the synchronization (TCK) and state control (TMS) signals from the test bus and generate the

appropriate on-chip control signals for the test structures in the device. Figure 2 shows the TAP-controller state

diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and

output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully

one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the

device contains an 8-bit instruction register and four test-data registers: a 52-bit boundary-scan register, a 3-bit

boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H

TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = H

TMS = L

Figure 2. TAP-Controller State Diagram