SN54GTL16622A, SN74GTL16622A

18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS

SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999

8

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature for GTL+ (unless otherwise noted)

SN54GTL16622A

SN74GTL16622A

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

200

200

MHz

tw

Pulse duration, CLK high or low

2.5

2.5

ns

t

Setup time

Data before CLK

↑

2.5

2.4

ns

tsu

Setup time

CE before CLK

↑

3.4

3.2

ns

th

Hold time

Data after CLK

↑

0.3

0.2

ns

th

Hold time

CE after CLK

↑

0.1

0

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature for GTL+ (see Figure 1)

PARAMETER

FROM

TO

SN54GTL16622A

SN74GTL16622A

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

fmax

200

200

MHz

tPLH

CLKAB

B

2.5

5.8

2.6

4

5.6

ns

tPHL

CLKAB

B

2.2

6.1

2.3

4

5.7

ns

tPLH

OEAB

B

2.3

5.5

2.4

3.8

5.2

ns

tPHL

OEAB

B

1.7

5.3

1.8

3.4

5

ns

Slew rate

Both transitions (B port)

0.5

0.5

V/ns

tr

Transition time, B outputs (0.6 V to 1.3 V)

0.9

2.8

1

1.6

2.7

ns

tf

Transition time, B outputs (1.3 V to 0.6 V)

0.4

3.7

0.5

1.1

3.2

ns

tPLH

CLKBA

A

1.9

5.5

2

3.8

5.3

ns

tPHL

CLKBA

A

1.8

5.3

1.9

3.6

5

ns

ten

OEBA

A

1.8

5.3

1.9

3.6

5

ns

tdis

OEBA

A

2

5.8

2.1

4

5.5

ns

† All typical values are at VCC = 3.3 V, TA = 25°C.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.