SN54HC594, SN74HC594

8-BIT SHIFT REGISTERS

WITH OUTPUT REGISTERS

SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998

7

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HC594

SN74HC594

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

5

8

3.3

4

fmax

4.5 V

25

35

17

20

MHz

6 V

29

40

20

24

2 V

50

150

225

185

SRCLK

QH

′

4.5 V

20

30

45

37

t d

6 V

15

25

38

31

ns

tpd

2 V

50

150

225

185

ns

RCLK

QA–QH

4.5 V

20

30

45

37

6 V

15

25

38

31

2 V

50

150

225

185

SRCLR

QH

′

4.5 V

20

30

45

37

tPHL

6 V

15

25

38

31

ns

tPHL

2 V

50

125

185

155

ns

RCLR

QA–QH

4.5 V

20

25

37

31

6 V

15

21

31

26

2 V

38

75

110

95

QH

′

4.5 V

8

15

22

19

tt

6 V

6

13

19

16

ns

tt

2 V

38

60

90

75

ns

QA–QH

4.5 V

8

12

18

15

6 V

6

10

15

13

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HC594

SN74HC594

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

90

200

300

250

tpd

RCLK

QA–QH

4.5 V

23

40

60

50

ns

6 V

19

34

51

43

2 V

90

200

300

250

tPHL

RCLR

QA–QH

4.5 V

23

40

60

50

ns

6 V

19

34

51

43

2 V

45

210

315

265

tt

QA–QH

4.5 V

17

42

63

53

ns

6 V

13

36

53

45

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

No load

395

pF

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design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.