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SN74LVC573A Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC573A Datasheet(HTML) 1 Page - Texas Instruments |
1 / 9 page SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCAS300I – JANUARY 1993 – REVISED JUNE 1998 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C D Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) D Power Off Disables Outputs, Permitting Live Insertion D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JESD 17 D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and DIPs (J) description The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. Copyright © 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. SN54LVC573A ...J OR W PACKAGE SN74LVC573A . . . DB, DW, OR PW PACKAGE (TOP VIEW) SN54LVC573A . . . FK PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1D 2D 3D 4D 5D 6D 7D 8D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2Q 3Q 4Q 5Q 6Q 3D 4D 5D 6D 7D On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. |
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