SN54LV74A, SN74LV74A

DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOPS

SCLS381L − AUGUST 1997 − REVISED APRIL 2005

2

POST OFFICE BOX 655303

description/ordering information (continued)

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H†

H†

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

Q0

Q0

† This configuration is nonstable; that is, it does not

persist when PRE or CLR returns to its inactive

(high) level.

logic diagram, each flip-flop (positive logic)

TG

C

C

TG

C

TG

C

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

C