SN54LVT8980, SN74LVT8980

EMBEDDED TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997

9

POST OFFICE BOX 655303

TDO

TMS

TCK

TDI

To

Other

Modules

Active Backplane (Motherboard)

Plug-In Module

’LVT8980

etBC

ASP

IEEE

Std

1149.1-Compliant

Device Chain

TRST

Plug-In Module

ASP

IEEE

Std

1149.1-Compliant

Device Chain

Plug-In Module

ASP

IEEE

Std

1149.1-Compliant

Device Chain

Figure 5. Active-Backplane (Motherboard) Application

architecture

Conceptually, the eTBC can be viewed as an IEEE Std 1149.1 coprocessor/accelerator that operates in

conjunction with (and under the control of) a host microprocessor/microcontroller. The eTBC implements this

function using an 8-bit generic host interface and a scan-test-based command/control architecture. As shown

in the functional block diagram, beyond these fundamental elements and another central block supporting

discrete-control mode, the eTBC functions are accomplished in four additional blocks – one for each of the

required TAP signals – a TCK generator, a TAP-state (TMS) generator, a TDO buffer, and a TDI buffer.

host interface

The eTBC host interface is implemented generically on an 8-bit read/write data bus (D7–D0). Three address

pins (A2–A0) directly index the eTBC’s eight read/write registers: configurationA, configurationB, status,

command, TDO buffer, TDI buffer, counter, and discrete control. The register address map is given in Table 1.

host access timing

Host access timing is asynchronous to the clock input (CLKIN) and is fully controlled by the read/write strobe

(STRB). The read/write select (R/W) serves to control the direction of data flow on the bidirectional data bus.

Figure 6 shows the read access timing while Figure 7 shows the write access timing. As shown, for either read

or write access, R/W and address signals should be held while STRB is low.

For read access (R/W high) the eTBC data bus outputs are made active, on the falling edge of STRB, to drive

the data contained in the selected eTBC register. Otherwise, when STRB is high, the eTBC data outputs are

at high impedance. Therefore, in many applications, the R/W signal can be shared in common with other host

peripherals (ROM or RAM, for example) while the STRB signal is generated separately (by discrete chip-select

signals available from the host or a decode logic) for each required peripheral.