ADP3121

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6

OD going high. If this second latch is set, then OVP is

must fall below UVLO.

Supply Capacitor Selection

bypass capacitor is recommended to reduce the noise and to

supply some of the peak currents that are drawn. Use a

4.7

mF, low ESR capacitor. Multilayer ceramic chip

(MLCC) capacitors provide the best combination of low

ESR and small size. Keep the ceramic capacitor as close as

possible to the ADP3121.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

can be selected after the high−side MOSFET is chosen. The

bootstrap capacitor must have a voltage rating that can

handle twice the maximum supply voltage. A minimum

50 V rating is recommended. The capacitor values are

determined by

(eq. 1)

+

(eq. 2)

where:

of 5 V to 10 V, 7 V being typical).

yields

For example, an NTD60N02 has a total gate charge of

ceramic capacitors should be used.

switch node. It also provides peak current limiting through

resistor needs to handle at least 250 mW due to the peak

currents that flow through it.

A small signal diode can be used for the bootstrap diode

bootstrap diode must have a minimum 15 V rating to

withstand the maximum supply voltage. The average

forward current can be estimated by

(eq. 3)

controller.

The peak surge current rating should be calculated by

(eq. 4)

MOSFET Selection

When interfacing the ADP3121 to external MOSFETs,

the designer should consider ways to make a robust design

that minimizes stresses on both the driver and the

MOSFETs. These stresses include exceeding the short time

duration voltage ratings on the driver pins as well as the

external MOSFET.

It is also highly recommended to use the Boot−Snap

circuit to improve the interaction of the driver with the

characteristics of the MOSFETs. If a simple bootstrap

arrangement is used, make sure to include a proper snubber

network on the SW node.

High−Side (Control) MOSFETs

A high−side, high speed MOSFET is usually selected to

minimize switching losses (see the ADP3186 or ADP3188

data sheet for Flex−Mode controller details). This typically

implies a low gate resistance and low input

capacitance/charge device. Yet, a significant source lead

inductance can also exist that depends mainly on the

MOSFET package; it is best to contact the MOSFET vendor

for this information.

The ADP3121 DRVH output impedance and the input

resistance of the MOSFETs determine the rate of charge

delivery to the internal capacitance of the gate. This

determines the speed at which the MOSFETs turn on and off.

However, because of potentially large currents flowing in

the MOSFETs at the on and off times (this current is usually

larger at turn−off due to ramping up of the output current in

the output inductor), the source lead inductance generates a

significant voltage when the high−side MOSFETs switch

off. This creates a significant drain−source voltage spike

across the internal die of the MOSFETs and can lead to a

catastrophic avalanche. The mechanisms involved in this

avalanche condition are referenced in literature from the

MOSFET suppliers.

The MOSFET vendor should provide a rating for the

maximum voltage slew rate at drain current around which this

can be designed. Once this specification is obtained,

determine the maximum current expected in the MOSFET by

(eq. 5)

where:

the driver. This current is divided roughly equally between

MOSFETs if more than one is used (assume a worst−case

mismatch of 30% for design margin).