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SN54LVTH373J Datasheet(PDF) 2 Page - Texas Instruments |
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SN54LVTH373J Datasheet(HTML) 2 Page - Texas Instruments |
2 / 7 page SN54LVTH373, SN74LVTH373 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS689E – MAY 1997 – REVISED APRIL 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH373 is characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74LVTH373 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L HL L L LX Q0 H X X Z logic symbol† 1D 3 1D 4 2D 7 3D EN 1 1Q 2 2Q 5 3Q 6 8 4D 13 5D 14 6D 4Q 9 5Q 12 6Q 15 OE 17 7D 18 8D C1 11 LE 7Q 16 8Q 19 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE To Seven Other Channels 1 11 3 2 LE 1D C1 1D 1Q |
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