NCP5395

http://onsemi.com

8

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Typ

Max

Unit

ERROR AMPLIFIER

Input Bias Current

−200

−

200

nA

Open Loop DC Gain

−

100

−

dB

Open Loop Unity Gain Bandwidth

−

18

−

MHz

Open Loop Phase Margin

−

70

−

°

Slew Rate

DC Load = ±125 mA to GND

−

10

−

V/ms

Maximum Output Voltage

10 mV of Overdrive,

3.0

−

−

V

Minimum Output Voltage

10 mV of Overdrive,

−

−

75

mV

Output Source Current

10 mV of Overdrive,

1.5

2.0

−

mA

Output Sink Current

10 mV of Overdrive,

0.75

1.0

−

mA

DIFFERENTIAL SUMMING AMPLIFIER

V+ Input Pull down Resistance

DRVON = low

DRVON = high

−

−

0.6

6.0

−

−

kW

V+ Input Bias Voltage

DRVON = low

DRVON = high

−

−

0.5

0.86

−

−

V

Input Voltage Range (Note 4)

−0.3

−

3.0

V

−3 dB Bandwidth

−

15

−

MHz

Closed Loop DC gain VS to Diffout (Note 4)

VS+ to VS− = 0.5 V to 1.6 V

0.98

1.0

1.02

V/V

Maximum Output Voltage

10 mV of Overdrive,

3.0

−

−

V

Minimum Output Voltage

10 mV of Overdrive,

−

−

0.5

V

Output Source Current

10 mV of Overdrive,

1.5

2.0

−

mA

Output Sink Current

10 mV of Overdrive,

1.0

1.5

−

mA

INTERNAL OFFSET VOLTAGE

Offset Voltage to the (+) Pin of the Error Amp & the

VDRP Pin

−2

0

+2

mV

3. Design guaranteed.

4. For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.

5. Guaranteed by design; not tested in production.

6. Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10

7. No DAC offset is implemented for AMD operation.