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SN65LVDS117DGG Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVDS117DGG Datasheet(HTML) 7 Page - Texas Instruments |
7 / 19 page SN65LVDS109, SN65LVDS117 DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS SLLS369C – AUGUST 1999 – REVISED MARCH 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.6 2.8 4.5 ns tPHL Propagation delay time, high-to-low-level output 1.6 2.8 4.5 ns tr Differential output signal rise time 0.3 0.8 1.2 ns tf Differential output signal fall time RL = 100 Ω, CL 10 pF 0.3 0.8 1.2 ns tsk(p) Pulse skew (|tPHL - tPLH|)‡ CL = 10 pF, See Figure 4 140 500 ps tsk(o) Output skew§ See Figure 4 100 550 ps tsk(b) Bank skew¶ 40 150 ps tsk(pp) Part-to-part skew# 1.5 ns tPZH Propagation delay time, high-impedance-to-high-level output 5.7 15 tPZL Propagation delay time, high-impedance-to-low-level output See Figure 5 7.7 15 ns tPHZ Propagation delay time, high-level-to-high-impedance output See Figure 5 3.2 15 tPLZ Propagation delay time, low-level-to-high-impedance output 3.2 15 ns † All typical values are at 25 °C and with a 3.3 V supply. ‡ tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. § tsk(o) is the magnitude of the time difference between the tPLH or tPHL of any outputs with both inputs tied together. ¶ tsk(b) is the magnitude of the time difference between the tPLH and tPHL of the two outputs of any bank of a single device. # tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. PARAMETER MEASUREMENT INFORMATION (VOY + VOZ)/2 IOZ IOY Y Z VOD VOY VOC VOZ VID VIB VIA IIA A B IIB Figure 1. Voltage and Current Definitions |
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