6

IMP8

RESET Output Operation

In µP/µC systems it is important to have the processor begin

operation from a known state or be able to return the system to a

known state. A RESET output to a processor is provided to pre-

vent improper operation during power supply sequencing or low

voltage – brownout – conditions.

The IMP811/812 are designed to monitor the system power sup-

ply voltages and issue a RESET signal when levels are out of

keeps RESET active for the reset timeout period, after which

RESET becomes inactive (HIGH for the IMP811 and LOW for the

IMP812).

To ensure that logic inputs connected to the IMP811 RESET pin

resistor at RESET is needed. The value is not critical.

Typically short duration transients of 100mV amplitude and 20µs

increases transient immunity.

Power

Supply

IMP811

VCC

GND

RESET

MR

100k

Ω

811/12_04.eps

Power

Supply

IMP812

VCC

GND

RESET

MR

100k

Ω

811/12_05.eps

Application Information

Reset Threshold

Suffix

Voltage (V)

L

4.63

M

4.38

J

4.00

T

3.08

S

2.93

R

2.63

becomes active. Alternatively, external circuitry or a human oper-

ator can initiate this condition using the Manual Reset (MR) pin.

There is an internal pullup on MR so it can be left open if it is not

used. MR can be driven by TTL/CMOS logic or even an external

switch, since it is already debounced. If the switch is at the end of

a long cable, it might require a bypass (100nF) at the pin if noise

pickup is a problem.

Six voltage thresholds are available to support 3V and 5V systems: