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SN74ABT3611 Datasheet(PDF) 6 Page - Texas Instruments |
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SN74ABT3611 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 26 page SN74ABT3611 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127E – JULY 1992 – REVISED APRIL 1998 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (continued) TERMINAL NAME I/O DESCRIPTION PEFB O (port B) Port-B parity error flag. When any byte applied to terminals B0 – B35 fails parity, PEFB is low. Bytes are organized as B0 – B8, B9 – B17, B18 –B26, and B27 – B35, with the most-significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of ODD/EVEN. The parity trees used to check the B0 – B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB low, ENB high, W/RB low, MBB high, and PGB high, PEFB is forced high regardless of the state of the B0 – B35 inputs. PGA I Port-A parity generation. Parity is generated for mail2 register reads from port A when PGA is high. The type of parity generated is selected by the state of ODD/EVEN. Bytes are organized as A0 – A8, A9 – A17, A18– A26, and A27 – A35. The generated parity bits are output in the most-significant bit of each byte. PGB I Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated is selected by the state of ODD/EVEN. Bytes are organized as B0 – B8, B9 – B17, B18 – B26, and B27 – B35. The generated parity bits are output in the most significant bit of each byte. RST I Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST is low. This sets AF, MBF1, and MBF2 high and EF, AE, and FF low. The low-to-high transition of RST latches the status of FS1 and FS0 to select AF and AE flag offset. W/RA I Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is high. detailed description reset The SN74ABT3611 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of the FIFO and forces the full flag (FF) low, the empty flag (EF) low, the almost-empty flag (AE) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be reset after power up before data is written to its memory. A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1. Table 1. Flag Programming FS1 FS0 RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) H H ↑ 16 H L ↑ 12 L H ↑ 8 L L ↑ 4 FIFO write/read operation The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0 – A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the A0 – A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FF is high (see Table 2). |
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