SN74ABT3613

64

× 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

6

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

NAME

I/O

DESCRIPTION

PEFB

O

(port B)

Port-B parity error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are

organized as B0–B8, B9–B17, B18–B26, and B27–B35 with the most-significant bit of each byte serving as the parity

bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by

the state of ODD/EVEN.

The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having CSB low, ENB

high, W/RB low, SIZ1 and SIZ0 high, and PGB high, the PEFB flag is forced high, regardless of the state of the

B0–B35 inputs.

PGA

I

Port-A parity generation. Parity is generated for data reads from the mail2 register when PGA is high. The type of

parity generated is selected by the state of ODD/EVEN. Bytes are organized as A0–A8, A9–A17, A18–A26, and

A27–A35. The generated parity bits are output in the most-significant bit of each byte.

PGB

I

Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity

generated is selected by the state of ODD/EVEN. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.

The generated parity bits are output in the most-significant bit of each byte.

RST

I

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

while RST is low. This sets the AF, MBF1, and MBF2 flags high and the EF, AE, and FF flags low. The low-to-high

transition of RST latches the status of the FS1 and FS0 inputs to select AF flag and AE flag offset.

SIZ0

SIZ1

I

(port B)

Port-B bus size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following

low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,

word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.

SW0

SW1

I

(port B)

Port-B byte swap selects. At the beginning of each long-word FIFO read, one of four modes of byte-order swapping

is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order

swapping is possible with any bus-size selection.

W/RA

I

Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a

low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.

W/RB

I

Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a

low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is high.

detailed description

reset

The SN74ABT3613 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four

port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device

reset initializes the internal read and write pointers of each FIFO and forces FF low, EF low, AE low, and the

AF high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FF is set high after two

low-to-high transitions of CLKA. The device must be reset after power up before data is written to its memory.

A low-to-high transition on the RST input loads the AF and AE offset register (X) with the value selected by the

flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

Table 1. Flag Programming

FS1

FS0

RST

AF/AE FLAG

OFFSET REGISTER (X)

H

H

↑

16

H

L

↑

12

L

H

↑

8

L

L

↑

4