SN74ABT3614

64

× 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS126H – JUNE 1992 – REVISED APRIL 2000

9

POST OFFICE BOX 655303

empty flags (EFA, EFB)

The FIFO empty flag is synchronized to the port clock that reads data from its array. When the empty flag is high,

new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted

FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when the fourth

byte or second word of the last long word is read.

The FIFO read pointer is incremented each time a new word is clocked to the output register. A word written

to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty-flag synchronizing

clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register

and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was

written. The FIFO empty flag is set high by the second low-to-high transition of the synchronizing clock and the

new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write

be the first synchronization cycle (see Figures 13 and 14).

full flags (FFA, FFB)

The FIFO full flag is synchronized to the port clock that writes data to its array. When the full flag is high, a

memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is

low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, the write pointer is incremented. From the time a word is read from a FIFO,

the previous memory location is ready to be written in a minimum of three cycles of the full-flag synchronizing

clock. A full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next

memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after

the read sets the full flag high and data can be written in the following clock cycle.

A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the

first synchronization cycle (see Figures 15 and 16).

almost-empty flags (AEA, AEB)

The FIFO almost-empty flag is synchronized to the port clock that reads data from its array. The almost-empty

state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with

one of four preset values during a device reset (see

reset ). An AE flag is low when the FIFO contains X or fewer

long words in memory and is high when the FIFO contains (X + 1) or more long words.

Two low-to-high transitions of the AE-flag synchronizing clock are required after a FIFO write for the AE flag to

reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more long words remains low

if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1)

level. An AE flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write

that fills memory to the (X + 1) level. A low-to-high transition of an AE flag synchronizing clock begins the first

Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 17 and

18).