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FTM-9412S-F20DCG Datasheet(PDF) 6 Page - Source Photonics, Inc. |
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FTM-9412S-F20DCG Datasheet(HTML) 6 Page - Source Photonics, Inc. |
6 / 11 page 2×5 SFF GEPON ONU Transceiver FTM-9412S-F20(i)(DC)G IEEE 802.3ah TM 1000BASE-PX20U Preliminary Data Sheet Apr. 2, 2007 Fiberxon Proprietary and Confidential, Do Not Copy or Distribute DS0000147-1a Page 6 of 11 Note A: Open emitter output internally. Note B: LVPECL output, AC coupled internally. Input stage in SerDes IC is assumed with high impedance and internal bias to Vcc-1.3V R1=R2=R3=R4=N.C, R5=100Ω Input stage in SerDes IC is assumed without internal bias to Vcc-1.3V R1=R2=82Ω,R3=R4=130Ω,R5=N.C Figure 3 shows the recommended interface schemes for FTM-9412S-F20(i)DCG GEPON MAC FTM-9412S-F20(i)DCG BM Laser Driver CM Limiting Amplifier Z=50 TD+(9) TD-(10) RD+(5) RD-(4) TX_BRST(8) SD(3) SerDes TXP TXN RX N RX P V CCT(6) V CCR(2) 2x1 uH 10 uF 0.1uF 0.1uF 0.1uF 10 uF V EET (7) V EER (1) PON_TX_DISABLE PON_LOS Z=50 Z=50 Z=50 +3.3V +3.3 V 10K 2x 150 R1 R2 R3 R4 R5 (Note B) (Note A) 130 130 82 82 +3.3V Figure 3 Recommended Interface Circuit (FTM-9412S-F20(i)DCG) Note A: Open emitter output internally. Note B: LVPECL output, AC coupled internally. Input stage in SerDes IC is assumed with high impedance and internal bias to Vcc-1.3V R1=R2=R3=R4=N.C, R5=100Ω Input stage in SerDes IC is assumed without internal bias to Vcc-1.3V R1=R2=82Ω,R3=R4=130Ω,R5=N.C |
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