1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

8Q

8D

7D

7Q

6Q

6D

5D

5Q

LE

DW OR N PACKAGE

(TOP VIEW)

SN74ALS533A, SN74AS533A

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SDAS270 – DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

Data Lines

Small-Outline (DW) Packages and Standard

Plastic (N) 300-mil DIPs

description

These 8-bit D-type transparent latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads.

They

are

particularly

suitable

for

implementing

buffer

registers,

I/O

ports,

bidirectional bus drivers, and working registers.

While latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is

taken low, the Q outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and

SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted

outputs.

A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic

levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive bus lines without

interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are off.

The SN74ALS533A and SN74AS533A are characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE

LE

D

Q

L

H

H

L

L

HL

H

L

LX

Q0

H

X

X

Z

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.