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SN74ALVCH162836DGV Datasheet(PDF) 6 Page - Texas Instruments |
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SN74ALVCH162836DGV Datasheet(HTML) 6 Page - Texas Instruments |
6 / 10 page SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122E – JULY 1997 – REVISED JUNE 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency † 150 150 150 MHz t Pulse duration LE low † 3.3 3.3 3.3 ns tw Pulse duration CLK high or low † 3.3 3.3 3.3 ns Data before CLK ↑ † 1.4 1.7 1.5 tsu Setup time Data before LE ↑ CLK high † 1.2 1.6 1.3 ns Data before LE ↑ CLK low † 1.4 1.5 1.2 Data after CLK ↑ † 0.9 0.9 0.9 th Hold time Data after LE ↑ CLK high or low † 1.1 1.1 1.1 ns † This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT (INPUT) (OUTPUT) MIN TYP MIN MAX MIN MAX MIN MAX fmax † 150 150 150 MHz A † 1 4.4 4.6 1.2 4 tpd LE Y † 1.1 5.8 6.1 1.4 5.1 ns CLK † 1 5.2 5.5 1.1 5 ten OE Y † 1.1 6.4 6.5 1.2 5.5 ns tdis OE Y † 1 4.7 5.2 1.7 5.1 ns † This information was not available at the time of publication. operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V UNIT PARAMETER TEST CONDITIONS TYP TYP TYP UNIT C d Power dissipation Outputs enabled CL =0 f=10MHz † 31.5 36 pF Cpd capacitance Outputs disabled CL = 0, f = 10 MHz † 8 10.5 pF † This information was not available at the time of publication. |
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