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AD7846KP Datasheet(PDF) 7 Page - Analog Devices |
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AD7846KP Datasheet(HTML) 7 Page - Analog Devices |
7 / 16 page AD7846 REV. E –7– VDD/VSS – Volts 0.5 11 1.0 12 13 14 15 TA = +25 C VREF+ = +5V VREF– = 0V GAIN = +1 1.5 2.0 2.5 3.0 3.5 4.0 16 Figure 13. Typical Linearity vs. VDD/VSS VDD/VSS – Volts 0 11 12 13 14 15 TA = +25 C VREF+ = +5V VREF– = 0V GAIN = +1 0.2 1.0 16 0.4 0.6 0.8 Figure 14. Typical Monotonicity vs. VDD/VSS CIRCUIT DESCRIPTION Digital Section Figure 15 shows the digital control logic and on-chip data latches in the AD7846. Table II is the associated truth table. The D/A converter has two latches that are controlled by four signals: CS, R/W, LDAC and CLR. The input latch is con- nected to the data bus (DB15–DB0). A word is written to the input latch by bringing CS low and R/W low. The contents of the input latch may be read back by bringing CS low and R/W high. This feature is called “readback” and is used in system diagnostic and calibration routines. Data is transferred from the input latch to the DAC latch with the LDAC strobe. The equivalent analog value of the DAC latch contents appears at the DAC output. The CLR pin resets the DAC latch contents to 000 . . . 000 or 100 . . . 000, depend- ing on the state of R/ W. Writing a CLR loads 000 . . . 000 and reading a CLR loads 100 . . . 000. To reset a DAC to 0 V in a unipolar system the user should exercise CLR while R/W is low; to reset to 0 V in a bipolar system exercise the CLR while R/W is high. R/ W CLR CS DB15 DB0 16 16 16 DAC DB15 RST DB15 SET DB14–DB0 RST 3-STATE I/O LATCH DB15–DB0 LATCHES LDAC Figure 15. Input Control Logic Table II. Control Logic Truth Table CS R/ W LDAC CLR Function 1 X X X 3-State DAC I/O Latch in High- Z State 0 0 X X DAC I/O Latch Loaded with DB15–DB0 0 1 X X Contents of DAC I/O Latch Available on DB15–DB0 X X 0 1 Contents of DAC I/O Latch Transferred to DAC Latch X 0 X 0 DAC Latch Loaded with 000 . . . 000 X 1 X 0 DAC Latch Loaded with 100 . . . 000 D/A Conversion Figure 16 shows the D/A section of the AD7846. There are three DACs, each of which have their own buffer amplifiers. DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor string but have their own analog multiplexers. The voltage refer- ence is applied to the resistor string. DAC3 is a 12-bit voltage mode DAC with its own output stage. The 4 MSBs of the 16-bit digital code drive DAC1 and DAC2 while the 12 LSBs control DAC3. Using DAC1 and DAC2, the MSBs select a pair of adjacent nodes on the resistor string and present that voltage to the positive and negative inputs of DAC3. This DAC interpolates between these two voltages to produce the analog output voltage. To prevent nonmonotonicity in the DAC due to amplifier offset voltages, DAC1 and DAC2 “leap-frog” along the resistor string. For example, when switching from Segment 1 to Segment 2, DAC1 switches from the bottom of Segment 1 to the top of Segment 2 while DAC2 stays connected to the top of Segment 1. The code driving DAC3 is automatically complemented to compensate for the inversion of its inputs. This means that any linearity effects due to amplifier offset voltages remain un- changed when switching from one segment to the next and 16-bit monotonicity is ensured if DAC3 is monotonic. So, 12-bit resistor matching in DAC3 guarantees overall 16-bit monotonicity. This is much more achievable than the 16-bit matching which a conventional R-2R structure would have needed. |
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