SN74ALVCH16827

20-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES041C – JULY 1995 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303

Widebus

™ Family

CMOS) Submicron Process

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Need for External Pullup/Pulldown

Resistors

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

This 20-bit noninverting buffer/driver is designed

The SN74ALVCH16827 is composed of two 10-bit

sections with separate output-enable signals. For

either 10-bit buffer section, the two output-enable

(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must

both be low for the corresponding Y outputs to be

active. If either output-enable input is high, the

outputs of that 10-bit buffer section are in the

high-impedance state.

To ensure the high-impedance state during power

through a pullup resistor; the minimum value of

the resistor is determined by the current-sinking

capability of the driver.

Active bus-hold circuitry is provided to hold

unused or floating data inputs at a valid logic level.

The SN74ALVCH16827 is characterized for

operation from –40

°C to 85°C.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG OR DL PACKAGE

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1OE1

1Y1

1Y2

GND

1Y3

1Y4

1Y5

1Y6

1Y7

GND

1Y8

1Y9

1Y10

2Y1

2Y2

2Y3

GND

2Y4

2Y5

2Y6

2Y7

2Y8

GND

2Y9

2Y10

2OE1

1OE2

1A1

1A2

GND

1A3

1A4

1A5

1A6

1A7

GND

1A8

1A9

1A10

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2A9

2A10

2OE2

EPIC and Widebus are trademarks of Texas Instruments Incorporated.