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FTM-9412S-F20FD Datasheet(PDF) 6 Page - Source Photonics, Inc. |
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FTM-9412S-F20FD Datasheet(HTML) 6 Page - Source Photonics, Inc. |
6 / 11 page 2×5 SFF GEPON ONU Diplexer FTM-9412S-F20F(G)/ FTM-9412S-F20FD(G) IEEE 802.3ah TM 1000BASE-PX20U Preliminary Data Sheet Mar. 16, 2007 Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Doc No: DS3493013-1f Page 6 of 11 Note A: Open emitter output internally. Note B: LVPECL output, AC coupled internally. Input stage in SerDes IC is assumed with high impedance and internal bias to Vcc-1.3V R1=R2=R3=R4=N.C, R5=100Ω Input stage in SerDes IC is assumed without internal bias to Vcc-1.3V R1=R2=82Ω,R3=R4=130Ω,R5=N.C Figure 3 shows the recommended interface schemes for FTM-9412S-F20FD(G) Figure 3 Recommended Interface Circuit (FTM-9412S-F20FD(G)) Note A: Open emitter output internally. Note B: LVPECL output, AC coupled internally. Input stage in SerDes IC is assumed with high impedance and internal bias to Vcc-1.3V R1=R2=R3=R4=N.C, R5=100Ω Input stage in SerDes IC is assumed without internal bias to Vcc-1.3V R1=R2=82Ω,R3=R4=130Ω,R5=N.C |
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