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SN74LVCH16373ADGGR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVCH16373ADGGR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 13 page SN74LVCH16373A 16BIT TRANSPARENT DTYPE LATCH WITH 3STATE OUTPUTS SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. terminal assignments 123456 A 1OE NC NC NC NC 1LE B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2LE NC − No internal connection FUNCTION TABLE INPUTS OUTPUT OE LE D OUTPUT Q L H H H L HL L L LX Q0 H X X Z GQL OR ZQL PACKAGE (TOP VIEW) A B C D E F G H J K 1 2345 6 |
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