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SN75C1154 Datasheet(PDF) 1 Page - Texas Instruments |
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SN75C1154 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 D Very Low Power Consumption 5 mW Typ D Wide Driver Supply Voltage . . . ±4.5 V to ±15 V D Driver Output Slew Rate Limited to 30 V/ µs Max D Receiver Input Hysteresis... 1000 mV Typ D Push-Pull Receiver Outputs D On-Chip Receiver 1-µs Noise Filter D Functionally interchangeable With Motorola MC145404 description The SN75C1154 is a low-power BiMOS device containing four independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device has been designed to conform to ANSI EIA/TIA-232-E. The drivers and receivers of the SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/ µs and the receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need for external components. The SN75C1154 is designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of the input signals. If this is not the case or for other uses, it is recommended that the SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. The SN75C1154 is characterized for operation from 0 °C to 70°C. logic symbol† 4DY 3DY 2DY 1DY 4RA 3RA 2RA 1RA 4DA 3DA 2DA 1DA 4RY 3RY 2RY 1RY 9 7 5 3 8 6 4 2 12 14 16 18 13 15 17 19 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) typical of each driver typical of each receiver DY RA DA RY 3, 5, 7, 9 2, 4, 6, 8 18, 16, 14, 12 19, 17, 15, 13 Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VDD 1RA 1DY 2RA 2DY 3RA 3DY 4RA 4DY VSS VCC 1RY 1DA 2RY 2DA 3RY 3DA 4RY 4DA GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DW OR N PACKAGE (TOP VIEW) |
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