TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996

11

POST OFFICE BOX 655303

receive timing requirements over recommended ranges of supply voltages and operating free-air

temperature, variable-data-rate mode (see Figure 6)

MIN

MAX

UNIT

td(TSDR)

Time-slot delay time from DCLKR (see Note 9)

140

td(DCLKR)–140

ns

td(FSR)

Frame-sync delay time

100

tc(CLK)–100

ns

tsu(PCM IN)

Receive data setup time

50

ns

th(PCM IN)

Receive data hold time

60

ns

tc(DCLKR)

Data clock period

488

15620

ns

t(SER)

Time-slot end receive time

0

ns

NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.

64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air

temperature, variable-data-rate mode

MIN

MAX

UNIT

tFSLX

Transmit frame-sync minimum down time

FSX = TTL high for remainder of frame

488

ns

tFSLR

Receive frame-sync minimum down time

FSX = TTL high for remainder of frame

1952

ns

tw(DCLK)

Pulse duration, data clock

10

µs

switching characteristics

delay time over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate

mode (see Figure 3 and 4)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd1

From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable

time on time-slot entry) (see Note 10)

CL = 0 to 100 pF

0

145

ns

tpd2

From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data

valid time)

CL = 0 to 100 pF

0

145

ns

tpd3

From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time

on time-slot exit) (see Note 10)

CL = 0

60

215

ns

tpd4

From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable

time)

CL = 0 to 100 pF

0

145

ns

tpd5

From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable

time) (see Note 10)

CL = 0

60

190

ns

tpd6

From rising edge of channel time slot to SIGR update (TCM29C14A and

TCM129C14A only)

0

2

µs

NOTE 10: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state.

delay time over recommended ranges of operating conditions, variable-data-rate mode (see Note 11 and

Figure 5)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd7

Delay time from DCLKX

0

100

ns

tpd8

Delay from time-slot enable to PCM OUT

CL = 0 to 100 pF

0

50

ns

tpd9

Delay from time-slot disable to PCM OUT

0

80

ns

tpd10

Delay time from FSX

td(TSDX) = 80 ns

0

140

ns

NOTE 11: Timing parameters tpd8 and tpd9 are referenced to the high-impedance state.