TIBPAL22V10-7C

HIGH-PERFORMANCE IMPACT-X

™ PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS014D – D3520, AUGUST 1990 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303

10

preload procedure for registered outputs (see Notes 3 and 4)

The output registers can be preloaded to any desired state during device testing. This permits any state to be

tested without having to step through the entire state-machine sequence. Each register is preloaded individually

by following the steps given below:

Step 3. Pulse pin 1, clocking in preload data.

level at the output pin.

td

tsu

tw

td

VIHH

VIL

VIL

VOL

VOH

VIH

Pin 13

Pin 1

Registered I/O

Input

Output

VIH

VIL

Figure 2. Preload Waveforms

NOTES: 3. Pin numbers shown are for the NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly.

4.