TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

5

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

NAME

NO.

FN

NO.

PM

I/O

DESCRIPTION

RD1

RD2

24

25

9

10

I

Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected, the CPU

is allowed to read status information or data from a selected ACE register. Only one of these inputs is required

for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied

low or RD1 tied high).

RI

43

38

I

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem

status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high

level since the last read from the modem status register. If the modem status interrupt is enabled when this

transition occurs, an interrupt is generated.

RTS

36

26

O

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS

is set to its active level by setting the RTS MCR bit and is set to its inactive (high) level either as a result of a

master reset, during loop mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS

is set to its inactive level by the receiver threshold control logic.

RXRDY

32

21

O

Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating

in the FIFO mode, one of two types of DMA signalling can be selected through the FIFO control register bit

3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports

single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA

in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0

(FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding

register, RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or

holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level

or the timeout has been reached, RXRDY goes active (low); when it has been active but there are no more

characters in the FIFO or holding register, it goes inactive (high).

SIN

11

55

I

Serial data. SIN is the input from a connected communications device.

SOUT

13

58

O

Composite serial data output to a connected communication device. SOUT is set to the marking (high) level

as a result of master reset.

TXRDY

27

13

O

Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,

one of two types of DMA signalling can be selected through FCR3. When operating in the TL16C450 mode,

only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU

bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the

transmit FIFO has been filled.

VCC

44

40

5-V supply voltage

VSS

22

8

Supply common

WR1

WR2

20

21

4

6

I

Write inputs. When either input is active (low or high respectively) and while the ACE is selected, the CPU is

allowed to write control words or data into a selected ACE register. Only one of these inputs is required to

transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or

WR1 tied high).

XIN

XOUT

18

19

1

2

I/O

External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

detailed description

autoflow control

Auto-flow control is composed of auto-CTS and auto-RTS. With auto-CTS, CTS must be active before the

transmit FIFO can emit data (see Figure 1). With auto-RTS, RTS becomes active when the receiver is empty

or the threshold has not been reached. When RTS is connected to CTS, data transmission does not occur

unless the receive FIFO has empty space. Thus, overrun errors are eliminated when ACE1 and ACE2 are

TLC16C750s with enabled autoflow control. If not, overrun errors occur if the transmit data rate exceeds the

receive FIFO read latency.